JTAG testing with XJTAG tools: Fast test development, Real-time chain validation & debug, Early design verification before layout, functional testing of non-JTAG devices.| XJTAG
Quick guide to JTAG Boundary Scan technology: Connection Testing, In-System Programming, BGA, Chain Integrity Testing, Functional Testing, Design for Test.| XJTAG
DFT techniques for making it possible to test hard-to-probe ICs using JTAG Boundary Scan, resulting in faster, lower cost manufacturing test| XJTAG
A Boundary Scan Description Language (BSDL) file is a subset of VHDL that describes how JTAG (IEEE 1149.1) is implemented in a particular device.| XJTAG