FPGA development and testing tools. See also Tutorials. Vivado Tcl Build Script - quick and easy Vivado builds with Tcl Verilog Simulation with Verilator and SDL - blazingly fast way to simulate your designs Verilog Lint with Verilator - quickly check your Verilog designs iCE40 FPGA Toolchain on Linux - building an open source FPGA toolchain for iCE40 FPGA Tooling on Ubuntu 20.04 - testing FPGA tools with Ubuntu 20.04 Focal Fossa| Project F
It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer.| Project F