FPGA development and testing tools. See also Tutorials. Vivado Tcl Build Script - quick and easy Vivado builds with Tcl Verilog Simulation with Verilator and SDL - blazingly fast way to simulate your designs Verilog Lint with Verilator - quickly check your Verilog designs iCE40 FPGA Toolchain on Linux - building an open source FPGA toolchain for iCE40 FPGA Tooling on Ubuntu 20.04 - testing FPGA tools with Ubuntu 20.04 Focal Fossa| Project F
Welcome back to Exploring FPGA Graphics. Last time, we got an introduction to FPGA graphics; let’s put our new graphical skills to work with some simple demo effects. I hope these examples inspire you to create your own effects and improve your hardware design skills.| Project F
Hardware design can be unforgiving, so it pays to use any advantage you can get. Verilator is a Verilog simulator and C++ compiler that also supports linting: statically analysing your designs for issues. Not only can Verilator spot problems your synthesis tool might overlook, but it also runs quickly.| Project F
Welcome to Exploring FPGA Graphics. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. Along the way, you’ll experience a range of designs and techniques, from memory and finite state machines to crossing clock domains and translating C algorithms into Verilog.| Project F
The Open Source Simulation Status Quo| Electronics etc…