The Translation Lookaside Buffer (TLB) is a cache of memory page translations employed in many systems with memory paging capability. When the processor needs to translate a given virtual address into a physical address, the TLB is consulted first. On x86 systems, TLB misses are handled transparently by hardware. Only if the page directory/table entry is not present in-core will the operating system be notified (by the means of a page fault exception.)| wiki.osdev.org
Stack can also refer to the TCP/IP stack in Networking. This article discuss the datastructure and stacks used in architectures. | wiki.osdev.org
A Task State Segment (TSS) is a binary data structure specific to the IA-32 and x86-64 architectures. It holds information about a task. In Protected Mode the TSS is primarily suited for Hardware Task Switching, where each individual Task has its own TSS. For use in software multitasking, one or two are also generally used, as they allow for entering Ring 0 code after an interrupt. In Long Mode, the TSS has a separate structure and is used to change the Stack Pointer after an interrupt or per...| wiki.osdev.org
This article discusses x86-64 CPUs (AMD64 and Intel's equivalent EM64T implementation). IA-64 (Itanium) is really a different beast and not addressed here.| wiki.osdev.org
Contents| wiki.osdev.org