Today’s @risc_v Tip: If using ld as your linker, a global symbol defined as start will take precedence over earlier symbols in your .text section for program entry point when explicit ENTRY is not defined in your script or via -e flag on the command line. Original Tweet| danielmangum.com
Today’s @risc_v Tip: Traps become more complicated in a pipelined implementation if exceptions occur after subsequent instructions have been issued. The sepc CSR holds the address of the offending instruction, but an implementation may choose whether it is precise or not. Original Tweet| danielmangum.com
Tonight’s @risc_v Tip: The satp CSR configures Supervisor (S) mode address translation and protection. RV32 and RV64 support different sets of virtual addressing schemes, which can be configured by writing MODE bits. Writing an unsupported scheme is ignored (WARL). Original Tweet| danielmangum.com
Tonight’s @risc_v Tip: An optional Physical Memory Protection (PMP) unit is defined that enables memory access control for software on a given hart. This is accomplished through a set of configuration and address CSRs, and applies to all accesses with effective mode of S or U. Original Tweet| danielmangum.com
This is part of a new series I am starting on the blog where we’ll explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. To start of the series, we are just going to get setup to do some exploration. I am going to assume you will not primarily be using a RISC-V machine1, so we need to configure our local development environment for cross-platform compiling, emulation, and debugging.| danielmangum.com
This is part of a new series I am starting on the blog where we’ll explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. When looking at the generated assembly for a function, you may have noticed that the first few instructions involve moving values from registers to the stack, then loading those values back into the same registers before returning.| danielmangum.com
This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page. So far in this series, we have been looking at the assembly generated when compiling relatively simple programs. At this point, we have seen instructions that perform a wide variety of operations. Let’s take another look at our minimal example from the Passing on the Stack post:| danielmangum.com