Synthesis converts a behavioral description of the circuit, in the form of RTL, into an equivalent netlist made of cells from the standard cell library. It is analogous to the compilation process used for turning programming languages like C into binaries. The compiler knows how to read the language and maps it to the instructions we have available in the CPU, and synthesis translates from what we want the design to do, into a set of available cells that will perform it.| Zero to ASIC Course
One of the many things a PDK contains is the standard cell library. This is a collection of all digital building blocks used to build an IC like AND, OR, NOT gates, flip-flops, etc. There will be other libraries for specialised functions such as IO pads, and any analogue blocks or memory macros, and so on. Standard cell libraries are a set of cells that have common characteristics and physical layout.| Zero to ASIC Course
A Hardware Description Language is used to… describe hardware! So instead of drawing out an inverter using a tool like Magic we can write a line like this: output = !input; Which describes what an inverter does. The ! means invert. This is a description of what the circuit does, similar to a programming language like C (although everything happens at once, not in sequence). This is referred to as a ‘Register Transfer Level’ or RTL.| Zero to ASIC Course
Place and Route are two steps in the automated process of turning some HDL into GDS2 files. We will look at how OpenLane does these steps using the seven segment seconds example. I have used my presentation tools to generate these images. Place Placement is done in two steps, coarse and fine. The coarse step puts the standard cells in roughly the right place. This may be referred to as global placement, or initial placment. The aim here is to minimise the estimated total wire length of all th...| Zero to ASIC Course
