RISC-V: Designing a RISC-V CPU in VHDL, Part 22: Doom as a benchmark and adding Cache to RPU Designing a RISC-V CPU in VHDL, Part 21: Multi-cycle execute for multiply and divide Designing a RISC-V CPU in VHDL, Part 20: Interrupts and Exceptions Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit Designing a RISC-V CPU in VHDL, Part 17: DDR3 Memory Controller, Clock domain crossing Designing a RISC-V...| domipheus.com
Low level software usually has lots of .cc or .rs files. Even lower-level software, like your cryptography library, probably has .S containing assembly, my least favorite language for code review.| mcyoung.xyz