MPW1 silicon has serious problems | Zero to ASIC Course
MPW1 seems an age ago, we submitted in December 2020, but it needed some last minute DRC fixes in February. Silicon was received a few weeks ago, and unfortunately we have some serious issues that will prevent most designs from working. This appears to be due to a bad clock tree in the management section of the chip. Additionally, OpenSTA, the tool meant to verify the clock tree was also misconfigured.| Zero to ASIC Course
