The VisionFive 2 is the first affordable all-inclusive RISC-V SBC. While it has some drawbacks, the low cost makes it great for solo devs.| magazin Mehatronika
VPR (pronounced “Viper”) is Nordic Semiconductor’s first RISC-V processor, landing in the new nRF54H and nRF54L lines of SoCs after their initial announcements in April and October of 2023 respectively. Readers of this blog are familiar with my long-running obsession interest in RISC-V (see my RISC-V Tips and RISC-V Bytes series). However, Nordic’s introduction of a RISC-V processor is particularly interesing to me as their lineup of microcontrollers is extremely popular in low power ...| danielmangum.com
VisionFive 2 je prvi pristupačan RISC-V SBC opšte namene. Iako ima neke nedostatke, niska cena ga čini odličnim za solo programere.| industrijski magazin
I am currently working on a few projects that involve leveraging WebAssembly (WASM) modules, particularly with WebAssembly System Interface (WASI) support. While WASI is still in its early stages, support has already been added to the Rust compiler and Clang, as well as runtimes such as wasmtime and WAMR. However, getting an environment setup to compile arbitrary C programs to WASM can still be challenging. I recently updated to Clang 17, which was first released as 17.| danielmangum.com
Note: all analysis and code samples used in this post correspond to the v3.3.0 release of Zephyr. Having a good debugging workflow is critical to developing software quickly with high confidence. Fortunately, writing software for computers is often done, well, on a computer, meaning that while writing programs we can run other programs that help us understand the behavior of what we are writing. Typically the machine we are writing software for, though it may run in a data center and have a d...| danielmangum.com
In the last two posts in the RISC-V Bytes series we have looked at a bootloader for the ESP32-C3, then built a Zephyr application that was loaded by it. In this post we’ll take a closer look at that “Hello, World” application, diving into what happens prior to printing our message to the UART console. Note: all analysis and code samples used in this post correspond to the v3.3.0 release of Zephyr.| danielmangum.com
Operating systems do great work, but sometimes they need a little bit of help to know when to switch from one task to another. Thankfully, hardware is there to help! Today we are going to take a look at how operating systems schedule reminders for themselves using timer interrupts. Sections Link to heading Don’t care about the why and just want to see the code? Jump ahead to The Full Picture.| danielmangum.com
If you write any code that deals with manual memory management, you are likely familiar with the concept of a “use after free” bug. These bugs can be the source of, at best, program crashes, and at worst serious vulnerabilities. A lesser discussed counterpart to use after free, is “use after return”. In some cases, the latter can be even more troublesome, due to the operations that are performed when one procedure calls another.| danielmangum.com
Sometimes I hear folks in the Crossplane community ask if they can just use Helm instead of opting into our package manager. The technical answer to this question is “yes”, but it typically represents a misinterpretation of what Crossplane is providing in a Kubernetes cluster. That being said, I completely understand why someone would ask this question, and quite frankly, I think the confusion is our fault. In Crossplane and across the Kubernetes community we lean in heavily to the idea t...| danielmangum.com