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I've been playing with the idea of running linux on ESP32 since the first days I've met its more robust module, the WROVER-B, on paper it seem possible since its a dual core 240Mhz and has 16MB flash and 8MB RAM, compared to our antique machines that could run linux, it seems like a beast.| Dror Gluska
The Godbolt Compiler Explorer is a fantastic tool for assembler programmers. In this post, I show you how to use Compiler Explorer to generate RISC-V assembly code and offer some ideas to make best use of this tool.| Project F
This cheat sheet provides a handy guide to 32-bit RISC-V instructions. I’ve aimed it at software developers, so group instructions by purpose and include common pseudoinstructions.| Project F
Integer multiply and divide instructions form the optional M extension. Making multiplication and division optional keeps the base instruction set simple and reduces the size of the smallest RISC-V core. This post includes a brief overview of common RISC-V extensions.| Project F
This RISC-V assembler post begins by examining the RISC-V jump instructions: jal and jalr. Jump instructions are the basis of functions, so we’ll then dig into function calls, the RISC-V ABI, calling convention, and how to use the stack.| Project F
This RISC-V assembler post covers branch and set instructions, such as beq, bltu, bgez, and slt. We’ll also cover the zero register, program counter, condition codes, and multi-word addition.| Project F
This RISC-V assembler post covers load and store instructions, such as lw, sw, and lbu. We also cover memory alignment, addressing modes, and loading symbol addresses.| Project F
This RISC-V assembler post covers shift instructions, such as sll, srl, and srai. I also explain how to use shift instructions to quickly multiply and divide by powers of two.| Project F
This RISC-V assembler post covers bitwise logical instructions, such as and, not, and xori. Bitwise instructions carry out the specified operator on each bit of the sources in turn.| Project F
This series will help you learn and understand 32-bit RISC-V instructions and programming. The first part looks at load immediate, addition, and subtraction. We’ll also cover sign extension and pseudoinstructions.| Project F
Contents Repository Introduction The APLIC Conclusion Repository This blog series refers to the code written here: https://github.com/sgmarz/riscv_msi. The APLIC specification (still in draft) is part of the Advanced Interrupt Architecture (AIA) specification, and it is kept here: https://github.com/riscv/riscv-aia. I am using AIA specification version 0.3.0-draft.31 to write this article. Introduction The advanced platform level interrupt […]| Stephen Marz
Contents Overview Repository Message Signaled Interrupts (MSI) Incoming MSI Controller (IMSIC) Conclusion What’s Next Overview Message signaled interrupts or MSIs describe a way to signal an interrupt without a dedicated interrupt request pin (IRQ). One of the most prevalent uses for MSIs is the PCI bus, and the PCI specification defines the MSI and MSI-X […]| Stephen Marz
Writing assembly is itself an art. When C, C++, or any other language is compiled, the compiler determines the art of writing assembly. However, this time, we will some of the techniques and decisions we can make to write these ourselves. We will use RISC-V to see how to design logic, write up the logic, […]| Stephen Marz
This post is part of a larger effort you can view over here: https://osblog.stephenmarz.com. Video Contents Overview Application Programmer’s Interface (API) Starting Routines System Calls Drawing Primitives Event Handling Start Our Game Game Loop PLAY Overview We last left off writing a graphics driver and an event driver for our operating system. We also added […]| Stephen Marz
This post is part of a longer OS tutorial which can be found here: https://osblog.stephenmarz.com Contents Introduction What is SATP? What is SFENCE.VMA? What is happening? The Translation Lookaside Buffer Conclusion References Introduction My last post garnered some attention by those telling me that I “forgot” to execute an SFENCE.VMA after I wrote to the […]| Stephen Marz
This is a continuation of an ongoing theme which is started here: https://osblog.stephenmarz.com. Contents What is Supervisor Mode? Why Supervisor Mode? Complications while in Supervisor Mode Complications with Interrupts Conclusion What is Supervisor Mode? My original OS Blog (see here: https://osblog.stephenmarz.com) ran the operating system in RISC-V’s machine mode, which is the most privileged mode […]| Stephen Marz
Introduction Last year, I got interested in FPGAs and purchased a Digilent Basys3, which was lots of fun to play with, I even got a minimal RISC-V processor programmed. The Basys3 is their lower en…| Stephen Smith's Blog
This article describes ABI and toolchain considerations about systems without a Memory Management Unit (MMU). We will focus on FDPIC and the in-development FDPIC ABI for RISC-V, with updates as I delv| MaskRay
For GD32VF103 (Note: it's not GD32 F 103, but GD32 VF 103), I ported| www.gniibe.org