bloke2 involves reversing a Verilog description language project to find a hidden flag inserted by a missing developer. I’ll find a relatively long string of data and where an XOR might be applying it to the input test data, except it’s always disabled by a flag. I’ll enable that flag and the flag comes out while running the tests.| 0xdf hacks stuff
I feel like if computers didn’t exist, I would have been a mathematician. But| astrid.tech
I am in the process of converting traditional verilog test benches to| A Scripter's Notes
Introduction Last year, I got interested in FPGAs and purchased a Digilent Basys3, which was lots of fun to play with, I even got a minimal RISC-V processor programmed. The Basys3 is their lower en…| Stephen Smith's Blog
Wiring my board up to an LCD screen on top of a copy of Hegel's Aesthetics. | k3170