Min-Yih "Min" Hsu's Personal Website| Min Hsu's Homepage
Introduction to machine scheduler & hazard detection| Min Hsu's Homepage
RISC-V Vector (RVV) extension has several kinds of load / store instructions which access memory in different ways. Just as the memory access pattern might take a little more time to fully understand, it gets even more tricky when multiplexing with RVV’s own concepts like variable element size (SEW), register groups (LMUL), number of elements (VL), masks and mask / tail policies. Personally I found it easier to memorize them with visualization, hence this (relatively) short post!| Min Hsu's Homepage
In the previous post, we covered the basics of scheduling model in LLVM. Specifically, per-operand tokens that connect an instruction with models that spell out processor-specific scheduling properties like instruction latency, and the concept of processor resources with different sizes of buffer. While I was planning to write how scheduling models are used in this post – namely, covering things like instruction scheduler and MCA – the draft was overwhelmed by the sheer amount of content ...| Min Hsu's Homepage
There is a nice page about how LLVM handles RISC-V Vector Extension (RVV). It primarily covers how the RISC-V backend lowers vector types and vector operations. Right at the beginning of the page lies this table: It shows the LLVM IR types we use to represent RVV’s dynamically sized vectors: each row is an element type, while each column is a LMUL – the register grouping factor, or “how many vector registers should we slap together and treat it as a single logical vector register”.| Min Hsu's Homepage
Instruction scheduling is essential to modern compilers. It tries to hide latencies and increases the throughput of a straight line code by reordering the enclosing instructions. In order to do that, compilers have to know a whole bunch of information, ranging from individual instruction’s latency to microarchitecture details. The system that describes these is called a scheduling model. In LLVM, a scheduling model is used by not just the instruction scheduler, but also target-specific opti...| Min Hsu's Homepage
Ideally, compilers can build a program for a wide variety of hardware without the need to change a single line of its source code. While there are exceptions and corner cases, this holds in the majority of cases. Which means that if the input code uses something that is not directly available on the hardware, the compiler has to figure out a way to effectively emulate those features. This might sound a little distant to our typical software development experiences, but I’m not even talking ...| Min Hsu's Homepage
Book Min-Yih Hsu. “LLVM Techniques, Tips, and Best Practices Clang and Middle-End Libraries: Design Powerful and Reliable Compilers Using the Latest Libraries and Tools from LLVM”. Packt Publishing (2021). Amazon Link. Paper and Talk Min-Yih Hsu, Felicitas Hetzelt, David Gens, Michael Maitland, and Michael Franz. “A Highly Scalable, Hybrid, Cross-Platform Timing Analysis Framework Providing Accurate Differential Throughput Estimation via Instruction-Level Tracing” In Proceedings of AC...| Min Hsu's Homepage
Compiler, uArch, and a little bit of...jigsaw puzzle?| Min Hsu's Homepage