Development environment courtesy of RISE| fprox.substack.com
Comeback of (somewhat) block floating-point| What are you optimizing for ? (fprox's substack)
When you need to reduce a vector into a scalar| What are you optimizing for ? (fprox's substack)
One vector extension to rule them all (or not): survey of existing and future RISC-V Vector ISA extensions.| What are you optimizing for ? (fprox's substack)
From 17'800 cycles down to ?| What are you optimizing for ? (fprox's substack)
A touch of low level programming| What are you optimizing for ? (fprox's substack)
It is all about computing in the right space (and using cheap transforms)| What are you optimizing for ? (fprox's substack)
Zvbc(32e) for the win| What are you optimizing for ? (fprox's substack)
A mini computer with full RISC-V Vector 1.0 Support| What are you optimizing for ? (fprox's substack)
Zba, Zbb, Zbc, Zbs, Zbkb, Zbkc, Zbkx and B extensions| What are you optimizing for ? (fprox's substack)
P3109, OCP OFP8 and challenges of small 8-bit FP formats| What are you optimizing for ? (fprox's substack)
Quick and dirty method to implement a vectorized non-linear function using RVV| What are you optimizing for ? (fprox's substack)
Survey of basic techniques to transform matrix layouts using RVV| What are you optimizing for ? (fprox's substack)
Leveraging RISC-V Vector to slow down SHA-3 software implementation| What are you optimizing for ? (fprox's substack)
RVV for those who find assembly too low level| What are you optimizing for ? (fprox's substack)
Extension for placeholder instructions| What are you optimizing for ? (fprox's substack)
Fast track extensions Zfbfmin, Zvfbfmin, Zvfbfwma| What are you optimizing for ? (fprox's substack)
Accurate user-mode base event counting over privilege mode flow diversion| What are you optimizing for ? (fprox's substack)
completing RISC-V floating-point capabilities| fprox.substack.com
