Post :: Arthur's blog
Adding MCP support to Aider via NixOS overrides| Arthur's blog
In software engineering the part I like the least is the actual typing of coding. LLMs provide a nice solution to this problem. With very precise prompting and the right documentation, code, text, … in the context the code output is very close to how I would write it. My preferred tool until now was aider. It works great, but the development pace seems to have slowed sadly. One of the latest innovation in the vibe coding space has been model context protocol. MCP is basically a standardized...| Arthur's blog
So here is where it all started. I'm working on a Rust project that makes heavy use of conditional compilation through cargo features. The codebase has chunks of code that are only compiled when certain features are enabled, like this: #[cfg(feature = "generate_templates")]mod cert; #[cfg(feature = "generate_templates")]mod code_gen; #[cfg(feature = "generate_templates")]mod csr; #[cfg(feature = "generate_templates")]fngen_init_devid_csr(out_dir: &str) { // ... implementation } The problem? M...| Arthur's blog
Serprog Serprog is a serial flasher protocol that allows a userspace program like flashprog to communicate over a serial connection like RS232, USB endpount or a TCP stream to a microcontroller which talks to flash chip to read, write or erase it. Serprog works for all kinds of different flash chips but in this article we'll focus on SPI NOR since those are ubiquitous nowadays. Picoprog at OSFC: using embassy as a multifunction device For OSFC 2024, 9elements hosted a coreboot workshop, which...| Arthur's blog
If you've ever developed embedded firmware, you know the pain: cryptic flashing tools, primitive debugging methods, and a workflow that feels decades behind modern software development. You write code, compile it, flash it to hardware through a complex toolchain, and then… hope it works. When it doesn't, you're stuck with blinking LEDs and printf debugging over UART. probe-rs fundamentally changes this experience by bringing the productive, familiar workflow of userspace development to the ...| Arthur's blog
As software developers, we spend our days creating objects, defining relationships, and modeling reality in code. But have you ever stopped to think about the philosophical implications of what we're doing? Enter ontology – a branch of philosophy that deals with the nature of being, existence, and reality. Understanding Ontology In philosophy, ontology asks fundamental questions like "What exists?" and "What are the relationships between different things that exist?" These might sound abstr...| Arthur's blog
I recently switched from Sway to Hyprland. The primary reason for this change was my interest in content creation. Hyprland can record single windows, whereas Sway can only record the entire screen or part of it. So far, the transition has been smooth until I encountered the following issue after waking it from suspend with the lid closed. My Use Case I have a laptop that is mostly connected to a docking station driving an external display. The lid remains closed, and I don't want the laptop ...| Arthur's blog
This post will review 2 llm options in emacs how I set them up. Ellama Your browser does not support the video tag. From ellama Ellama is a tool for interacting with large language models from Emacs. It allows you to ask questions and receive responses from the LLMs. Ellama can perform various tasks such as translation, code review, summarization, enhancing grammar/spelling or wording and more through the Emacs interface. Ellama natively supports streaming output, making it effortless to use ...| Arthur's blog
Aider + Claude Sonnet 3.5 This morning, I needed a timer to spend only 10 minutes reading a book. I searched for CLI tools but couldn't find anything immediately that suited my needs due to laziness. So, I decided to write one myself with the help of AI. Using Aider coupled with Claude Sonnet 3.5, I was able to get something working on the first try. Afterward, I added a few features:| Arthur's blog
This whitepaper makes the case that UEFI firmware and more specifically EDK2 based solutions, be it open or the more ubiquitous closed ones, hurt business by driving up cost and delaying time to market, while at the same time are the root cause of more and more security problems. This whitepaper will contrast this UEFI status quo with other existing solutions like LinuxBoot in combination with coreboot, which fully embrace open source development, are scoring better on all those metrics. This...| Arthur's blog
Hi I'm Arthur. I do a lot of firmware hacking both professionally and in my spare time. My interests are very wide. Here is a non exclusive list: embedded software electronics physics chemistry pharmacology philosophy religion psychology biology fitness bright and colorful decoration using LEDs and lasers car and motorcycle mechanics science fiction & fantasy| Arthur's blog
github.com/ArthurHeymans| Arthur's blog
Rust in coreboot? Rust is a programming language with emphasis on performance, type safety and concurrency. It enforces memory safety at compile time. Unlike the C standard which is a 700+ page document, with a LOT of documented undefined behavior, rust has no undefined behavior unless the unsafe keyword is used. Zero cost abstractions make rust binaries very efficient in both size and execution, in places where C will have a hard time to be optimized (e.g. function pointers in structs).| Arthur's blog
This blog enty first appeared on the 9esec blog. A new toy to play with OpenBMC I wanted to play around with OpenBMC on a physical board and this article led me to the ASRock E3C246D4I. It's a not overly expensive Intel Coffee Lake board featuring an Aspeed AST2500 BMC. So the first thing I did was to compile OpenBMC. My computer was in for a quite a chore there. It needed to download 11G of sources and compile those. Needless to say this takes a long time on a notebook computer and is best d...| Arthur's blog
This blog enty first appeared on the 9esec blog. FSP-T in open source projects X86 CPUs boot up in a very bare state. They execute the first instruction at the top of memory mapped flash in 16 bit real mode. DRAM is not avaible (AMD Zen CPUs are the exception) and the CPU typically has no memory addressable SRAM, a feature which is common on ARM SOCs. This makes running C code quite hard because you are required to have a stack. This was solved on x86 using a technique called cache as ram or ...| Arthur's blog
This blog enty first appeared on the 9esec blog. I started working for 9elements in October 2020 and my first assignment was to get Intel CBnT working on the OCP Deltalake using coreboot firmware. Intel Converged Bootguard and TXT is a hardware assisted method to set up a root of trust. In this blog post I will discuss some of the changes needed in coreboot to get this working. Setting CBnT up properly was definitely a challenge, but the work did not stop there. So while Intel CBnT provides a...| Arthur's blog
Coreboot is migrating platforms from a romcc bootblock to C_ENVIRONMENT_BOOTBLOCK in which Cache-as-Ram is set up in the bootblock. When migrating Braswell, chromebooks featuring this SOC did not boot anymore while other boards did. Google uses a different FSP binary than the one present in the Intel Github FSP repository. Previously the romcc bootblock set up caching of the ROM, located microcodes and performed the update before calling FSP TempRaminit.| Arthur's blog
This explains a bit of history on CAR in coreboot and how it works. Glossary CPU cache: CPU cache is a piece of fast memory used by the CPU to cache access to things accessed in the CPU's linear memory space. This includes for DRAM, PCI BARs, the boot flash. Cache-as-RAM/CAR: Using not memory mapped CPU cache as execution environment. XIP: Execute in place on a memory mapped (read only) medium. SRAM: Static Random Access Memory, here: memory mapped memory that needs no initialization. ROMCC: ...| Arthur's blog
Written in Go, Hugo is an open source static site generator available under the Apache Licence 2.0. Hugo supports TOML, YAML and JSON data file types, Markdown and HTML content files and uses shortcodes to add rich content. Other notable features are taxonomies, multilingual mode, image processing, custom output formats, HTML/CSS/JS minification and support for Sass SCSS workflows. Hugo makes use of a variety of open source projects including: https://github.com/yuin/goldmark https://github.c...| Arthur's blog
What is so special about the x60 when running vendor bios? Vendor BIOS write protects its bootblock, which means the lowest 64K of the flash can’t be modified This is a problem since the first code that runs on the CPU comes from there and if we ever want to run coreboot the cpu must start with coreboot code. This write protection is set in the PBR (protect bios range) registers on the southbridge, there is currently no known way to change them back once they are locked by setting the SPI C...| Arthur's blog
So here is where it all started. I have this apple branded atheros AR5BXB92, with an ar9280 chipset, which is supported by the ath9k Linux drivers. This chipset is supposed to support both 5GHz and 2.4GHz frequencies, but using the wavemon tool 5GHz SSID never show up even when I'm next to a device that emits one. iw list shows the following: Band 2: Capabilities: 0x11ce HT20/HT40 SM Power Save disabled RX HT40 SGI TX STBC RX STBC 1-stream Max AMSDU length: 3839 bytes DSSS/CCK HT40 Maximum RX...| Arthur's blog
This post will explain a bit how the Intel 4 series DDR3 raminit came to be and will introduce a new board that can make use of this code, namely the Intel DG41WV. DDR3 raminit In the past I have worked quite on a bit on the coreboot code that support the Intel 4 series desktop chipset (those chipsets go by the name of G41, G43, G45, Q43, Q45, P41, P43, P45, B43 with each having a somewhat different feature set). In the past I have made quite a few improvements to the coreboot code for this p...| Arthur's blog
Introduction to panics in rust Undefined behavior (UB) is one of the most dangerous issues in systems programming, leading to crashes, security vulnerabilities, and unpredictable results. Rust prevents UB by panicking - forcefully stopping the program - when potentially unsafe operations are detected. Panics are Rust's way of handling unrecoverable errors. Unlike Result which handles expected errors, panics occur when: Array bounds are exceeded Integer overflow in debug mode Explicit calls to...| Arthur's blog
