RISC-V International
RISC-V is an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration.| RISC-V International
Introduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may overlook corner case and simulation-resistant...| RISC-V International
The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), edge computing, automotive, and industrial...| RISC-V International
by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly every five to six months, but...| RISC-V International
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As a participant at the recent RISC-V Summit in Shanghai, I witnessed firsthand the sheer scale and unwavering resolve with which China is strategically investing in and developing its domestic...| RISC-V International
Silicon Valley, CA – August 6th, 2025 – Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. RiscFree provides comprehensive visibility and...| RISC-V International
Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting...| RISC-V International
Raja Koduri, a legendary GPU architect from ATI Technologies, AMD, Apple, and Intel, on Tuesday said he had founded a new GPU startup that emerged from stealth mode today. Oxmiq Labs is...| RISC-V International
As modern space missions evolve in complexity, the role of software onboard spacecraft is undergoing a dramatic transformation. Spacecraft are no longer limited to basic telemetry and remote control. Today, onboard computing must support autonomous decision-making, intelligent data reduction, and rapid responses to unforeseen conditions—all while operating under strict constraints on power, size, and reliability. Artificial intelligence and machine learning (AI/ML) are the technologies dr...| riscv.org
By setting a clear, stable standard, the RVA23 profile’s ratification is spurring top vendors to align on a common RISC-V hardware goal. All we need now is that hardware. By...| RISC-V International
With IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every automotive leader should have on their LiDAR.| riscv.org
With the RISC-V software stack now maturing at pace, the cost of skipping the upstream has never been higher. I talk to the Linux leaders working to ensure code hits the kernel before silicon hits shelves.| riscv.org
RISC-V is an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration.| RISC-V International
Vector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads including AI/ML & cryptography, and enterprise hardware, operating systems and software workloads| riscv.org
On June 14th, 2024, the Eldorado Research Institute in Campinas, São Paulo, hosted the RISC-V Brazil event. This gathering brought together over 200 professionals, researchers, and students from 86 different companies, both private and public. Among the attendees was Luciana Santos, the Brazilian Minister of Science, Technology and Innovation, who emphasized the importance of Brazil’s membership in RISC-V International.| RISC-V International
Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities| RISC-V International
