Verification covers all areas of checking that a design, at some stage in the design process, is correct. This includes simulation, STA, DRC, LVS, LEC and other checks that are performed. In essence, any step that looks at the design, compares it with some other quantity, and does not alter the design, is part of verification. Simulation offers us a way of checking the design is doing what we expect functionally, but that is almost exactly why simulation on its own isn’t enough. When we sim...
