I’m working on a six-layer PCB with the following stackup: L1: Top (signals) L2: GND L3: Signal L4: PWR L5: GND L6: Bottom (signals) Some high-speed signals (USB3 differential pairs and a 4-bit SDIO bus) had to be routed on L3 due to space constraints. To maintain return paths, I’ve added stitching vias near signal vias when moving between layers. My question is: since L2 and L4 are both solid reference planes, do I also need stitching capacitors at the start and end of these L3 traces? O...
