A netlist is a machine readable file that contains all the connections between all the components in your design. They are one of the outputs of a Synthesis tool like Yosys. These examples are taken from http://bygone.clairexen.net/yosys/screenshots.html If you have a counter design written in an HDL like Verilog module counter (clk, rst, en, count); input clk, rst, en; output reg [3:0] count; always @(posedge clk) if (rst) count <= 4'd0; else if (en) count <= count + 4'd1; endmodule The outp...
