This article proposes a source driver integrated circuit (SD-IC) with a pixel compensator designed to minimize both silicon area and power consumption for organic light-emitting diode (OLED) displays. The proposed… The post An Area and Power Efficient Source Driver IC With Multi-Line Sensing Real-Time Pixel Compensation for OLED Displays appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
The challenge of evolving to create a memory that is shrinking compared to the previous generation while satisfying the high performance and low power required for flash memory has been… The post A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
The 3-D Gaussian splatting (3DGS), based on a machine learning-driven radiance field technique, is rapidly emerging as a next-generation solution in 3-D graphics. Owing to its short modeling time, computational… The post IRIS: An Energy-Efficient Spatial Computing SoC for Real-Time Interactive Rendering and Modeling With Surface-Aware 3-D Gaussian Splatting appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
We present a framework for design technology co-optimization (DTCO) of the main memory system with 1T1C FERAM as an alternative to DRAM. We start with the ferroelectric capacitor device model… The post Benchmarking of FERAM based memory system by optimizing ferroelectric device model appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
This paper presents a flexible and energy-efficient RISC-V System-on-Chip (SoC) in 22nm FinFET technology, achieving state-of-the-art performance by tightly integrating the CPU with a synthesized embedded FPGA (eFPGA), enabling the… The post A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
This article presents a biopotential recording analog front-end (AFE) specifically tailored for a two-electrode measurement system, capable of capturing small biopotential signals while tolerating a large common-mode interference (CMI) over… The post A 4.6 μW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
In this article, we propose a wideband mixer-first receiver with improved in-band (IB) linearity. It uses bootstrapped N-path mixer switches to achieve a constant on-state gate–source voltage for large IB… The post A 1-8 GHz, 190MHz BB BW Mixer-First Receiver With Bootstrapped Mixer Switches Achieving Over 16dBm In-Band IIP3 appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
The ferroelectric field-effect transistor (FeFET) is a promising memory device technology due to desirable attributes such as fast access times, high memory cell density, good endurance, compatibility with CMOS process,… The post A Bit-Cell Failure Analysis Framework For Ferroelectric Field-Effect Transistor-Based Memories appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area gains (PPA) in sub-3nm nodes. This work exploits… The post Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society