The increasing adoption of chiplet-based architectures highlights the compelling paradigm of disaggregating monolithic systems into interconnected chiplets, offering numerous advantages for heterogeneous integration. This disaggregation is essential as chips approach… The post A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
This article presents a stochastic analog Boolean satisfiability (SAT) solver, featuring a fast open-loop architecture with continuous-time (CT) self-loopback pull-up switches, a discrete-time (DT) scrambling scheme, and a cost-efficient hybrid… The post A Stochastic Analog Boolean Satisfiability Solver appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
This work describes a direct-conversion IQ receiver (RX) that does not utilize any active linear (power) amplification, covering its design considerations, prototype implementation, and measurement verification. Only RLC components, MOS… The post A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
Nonvolatile compute-in-memory (nvCIM) macros integrate memory and computation to enable high-density multiply-and-accumulate (MAC) acceleration for inference tasks on low-power edge artificial intelligence (AI) devices. Bayesian neural networks (BNNs)—which represent weights… The post A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
This article describes a single-ended (SE) clock-referenced PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance… The post A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
In this work, for the first time, we present a SPICE-compatible compact model of ferroelectric (FE) diodes to enable their design exploration for diverse applications, including memory and unconventional computing… The post A SPICE-Compatible Compact Model of Ferroelectric Diode appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
This work presents a comparative analysis of Complementary Field-Effect Transistor (CFET) and Nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHE), Negative Bias Temperature Instability (NBTI), Hot Carrier… The post Impact of Aging, Self-Heating and Parasitics Effects on NSFET and CFET appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
This paper introduces a framework that establishes a cohesive link between first principles-based simulations and circuit-level analyses using a machine learning-based compact modeling platform. Starting with atomistic simulations, the framework… The post Integrating Atomistic Insights with Circuit Simulations via Transformer-Driven Symbolic Regression appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society
We explore the effects of layered geometries of two-dimensional (2D) quantum spin systems as a method to tune and control material properties for spintronic devices. We analyze the dispersion relation… The post Quantum Field Theory Model for Spin-based Devices Using 2D van der Waals Materials appeared first on IEEE Solid-State Circuits Society.| IEEE Solid-State Circuits Society