This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs. The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More The post WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design appeared first on SemiWiki.| SemiWiki
As modern computing systems evolve toward greater parallelism, multithreaded and distributed architectures have become the norm. While this shift promises increased performance and scalability, it also introduces a fundamental challenge: debugging concurrent code. The elusive nature of race conditions, deadlocks, … Read More The post Taming Concurrency: A New Era of Debugging Multithreaded Code appeared first on SemiWiki.| SemiWiki
GenAI is certainly changing the world. Every day there are new innovations in the use of highly trained models to do things that seemed impossible just a short while ago. As GenAI models take on more tasks that used to be the work of humans, there is always a nagging concern about accuracy and bias. Was the data used to train the model … Read More The post Perforce Webinar: Can You Trust GenAI for Your Next Chip Design? appeared first on SemiWiki.| SemiWiki
I have seen a flood of verification announcements around directly reading product specs through LLM methods, and from there directly generating test plans and test suite content to drive verification. Conceptually automating this step makes a lot of sense. Carefully interpreting such specs even today is a largely manual task, requiring painstaking attention to detail…| Semiwiki
Please join us at the Design Automation Conference 2025 where we will highlight the company’s wide range of EDA products and semiconductor IP targeting, Power Devices, Automotive, Memory, Displays, HPC, 5G / 6G, and IoT applications. When: June 23 – 25, 2025, Exhibit Hours: 10:00 AM PDT – 6:00 PM PDT Where: Moscone Center West,…| Semiwiki
A new technical paper titled “QiMeng: Fully Automated Hardware and Software Design for Processor Chip” was published by researchers at Chinese Academy of Sciences. Abstract “Processor chip design technology serves as a key frontier driving breakthroughs in computer science and related fields. With the rapid advancement of information technology, conventional design paradigms face three major... » read more| Semiconductor Engineering
At the Design Automation Conference (DAC) 2025 in San Francisco, LUBIS EDA returns as an exhibitor to showcase its latest innovations in formal verification automation, helping semiconductor teams move faster and with more confidence through the most complex verification challenges. LUBIS EDA is a fast-growing EDA startup based in Germany, dedicated to unlocking the full…| Semiwiki
There is a built-in challenge for edge AI intended for long time-in-service markets. Automotive applications are the obvious example, while aerospace and perhaps medical usage may impose similar demands. Support for the advanced AI methods we now expect – transformers, physical and agentic AI – is not feasible without dedicated hardware acceleration. According to one…| Semiwiki
Modern SoCs can be complex with hundreds to thousands of IP blocks, so there’s an increasing need to have a front-end build and assembly methodology in place, eliminating manual steps and error-prone approaches. I’ve been writing about an EDA company that focuses on this area for design automation, Defacto Technologies, and we met by video…| Semiwiki
Cadence, a DAC 2025 industry sponsor, will exhibit in booth 1609 at the 62nd Design Automation Conference at San Francisco's Moscone West Convention Center. Highlights: Paul Cunningham, SVP and GM of the System Verification Group, Cadence, will speak at Cooley’s DAC Troublemaker Panel. This discussion will be an open Q&A covering interesting and even controversial…| Semiwiki
Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage.| Tech Design Forum
The 70th annual IEDM is putting together its next conference under the theme under the theme “shaping tomorrow’s semiconductor technology”.| Tech Design Forum
Dieter Therssen obtained his master's degree in Electronics Engineering from KU Leuven in 1987. He started his career as a hardware design engineer, using IMEC’s visionary tools and design methodologies in the early days of silicon integration. Since then, Dieter developed his career across many digital technologies, in a broad range of applications and for…| Semiwiki
This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.| Tech Design Forum
The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.| Tech Design Forum
Wrote a new Javascript framework. Do check it out. # Icarus Icarus is a JavaScript framework, that will enable you to write highly decoupled, yet structured web apps. Icarus is built on top of Twit…| Ameya Karve's Weblog
FOR IMMEDIATE RELEASE| wdc65xx.com
How Startups are doing different from mid/large size company? Salary? Work Opportunity?| Ankur | NLP Enthusiast
