LibreLane makes a lot of output files! This can be quite confusing when you’re getting started. Here’s a useful spreadsheet I made to show: the path of the files most important files and what they mean which tool creates which file Thanks Amr and Ahmed for helping me with this! The spreadsheet was updated for LibreLane in 2025. LibreLane summary tool I’ve also made a summary tool: https://github.com/mattvenn/librelane_summary This allows you to easily:| Zero to ASIC Course
This is one of the first projects I hardened using OpenLane. News update: my clock works! And you can buy a kit here! Still can't quite believe I have a clock on my desk that is powered by a chip I designed! pic.twitter.com/O5c2omQYYp — Matthew Venn (@matthewvenn) March 31, 2022 It shows the time on an LCD panel. It will be part of my first tapeout. After running the OpenLane ASIC flow, it results in a design that uses 180x180 microns (32000 square microns). As we have about 10e6 square mic...| Articles on Zero to ASIC Course
The Google/Skywater Shuttle has about 10 square mm of space for your project. This sounds tiny but is actually HUGE for many beginner projects. Read this post to find out what you could fit in the user space. For the Zero to ASIC course, I want to aggregate all your designs together into that area, so we need to do some extra bits: Multiplex all the inputs and outputs of your project to the GPIO pins of the Caravel harness. Connect important signals like clocks and make sure the tools know th...| Articles on Zero to ASIC Course
Since I started my channel in December 2020, I’ve posted 181 videos that have been watched 660k times for a total of 35k hours! To celebrate reaching 20k subscribers I wanted to share some of the ones I’m especially proud of, and why they matter to me. I’d say my all time favourite was when I used a particle accelerator to look inside my own microchips! I met Tomas Aidukas at the Free Silicon Conference. In his talk, he showed an amazing 3D view inside a microchip - captured using a tec...| Zero to ASIC Course
For the past two years, I’ve used GitHub Actions to automatically test the install instructions for the Zero to ASIC course. Now, as I work on a major update, I’m taking it further: I’m adding CI tests for every one of the 10 practical projects. The goal? Make sure students never run into out-of-date instructions or broken software. To do this, I’ve been exploring Harald’s IIC-OSIC-TOOLs Docker image and built a new composite GitHub Action.| Zero to ASIC Course
Parts Open the bag carefully and pour out the parts. You should have 11 pieces and a sticker. The parts are made to push fit together. They will wear out if you take it apart and rebuild it more than a couple of times. Diffusion This model is of a CMOS inverter. The C stands for complementary, and it means we use both N and P type MOSFETS in a complementary pair.| Zero to ASIC Course
Wow what a year! In this post I’m going to look back over 2024 and share some of my highlights and the goals I met and failed. Then I’ll share my ambitions and predictions for 2025. With all the open source tapeouts, events, workshops and news, there’s a ton to cover - so let’s jump in! 2024 Goals More people I aimed for 2000 new people to get started with open source silicon via my courses and tiny tapeout.| Zero to ASIC Course
It’s become a cliche, but hardware is hard! One reason why hardware is harder than software is that the time between revisions is often longer. We need to wait for new PCBs, or for components to be delivered. Or for more new PCBs after we realise we got it wrong! Another reason is that it can be expensive, and not just for the physical components. We generally need more of a lab than software developers. Not just soldering irons and good lighting. Test gear is essential for learning how you...| Articles on Zero to ASIC Course
Our first COB (chip on board) chips are working! This has been a dream of mine for a few years, and it’s finally a reality! We’re used to seeing chips as little black boxes on a circuit board, but what’s inside? The first part of the journey started with Tamas creating this cool circuit board. Then Stuart visited an old friend’s wire bonding factory in the outskirts of Shenzhen. It’s nothing like you might imagine. While IC manufacturing itself requires a very strict level of cleanl...| Articles on Zero to ASIC Course
Tiny Tapeout 9 closed with 95% utilisation! Look at this beauty! You can download the full resolution image here. TT09 was our best ever run, with 369 designs submitted from 21 countries. Among the digital projects we had an Atari 2600 (with games), a wide range of CPUs and even some SDR projects. On the analog side we had PLLs, opamps, ADCs, DACs and time to digital converters. For all the projects, check the chip’s page. I printed the datasheet, and it’s hefty! Download it here.| Articles on Zero to ASIC Course
In my recent video Getting started with open source ASICs, I provided an overview of the open-source silicon movement, highlighting key resources and tools while showcasing some inspiring projects. The video starts by looking back at the game-changing moment in 2020 when Google, Tim Ansell, and Efabless announced their free shuttle program, making it possible for anyone to get their open-source chip designs manufactured. This sparked a wave of innovation, with many taking their first steps in...| Articles on Zero to ASIC Course
This article will give you some insight into my journey into the world of analog microelectronics, as told in my recent talk at ORConf 2024. Back in 2020, inspired by Tim Ansell’s announcement of free tapeouts, I jumped headfirst into the world of open-source ASIC design. My first chip was a digitally focused project, reflecting my background in FPGA programming. It was amazing to see the power of digital abstraction—designing with ones and zeros, instantiating tons of transistors with a ...| Articles on Zero to ASIC Course
In this interview, I met up with Michael from Zeptobars in Zurich, Switzerland, where we use acid to decapsulate one of my Tiny Tapeout chips. This technique involves using acid to remove the protective epoxy layer of a chip, revealing the silicon die underneath. Decapping is commonly used to analyse the construction of integrated circuits. Michael usually decapsulates chips designed by others, sometimes decades ago, but this time one of the designs is his own.| Articles on Zero to ASIC Course
I’m very happy to announce that my paper about Tiny Tapeout has just been published by the IEEE solid state circuits magazine! Tiny Tapeout aims to make it easier and cheaper than ever to design and manufacture custom Application-Specific Integrated Circuits (ASICs). I originally conceived of the idea in September 2022 as a way to guarantee silicon for my course participants. If you’re an IEEE member, you can read it here: https://ieeexplore.ieee.org/document/10584359, otherwise you can r...| Articles on Zero to ASIC Course
Tiny Tapeout 6 marked a significant milestone by introducing support for analog and mixed-signal ASIC designs. This innovation opened up a world of possibilities for open-source chip development, building on the project’s success in the digital realm. Prior to Tiny Tapeout 6, only digital designs were supported. However, the demand for analog and mixed-signal capabilities was evident. In an interview, Carsten Wulff, Principal IC Scientist at Nordic Semiconductor, expressed his enthusiasm fo...| Articles on Zero to ASIC Course
In this insightful interview, I talk with Carsten Wulff, Principal IC Scientist at Nordic Semiconductor, about all things analog ASIC design. Carsten kicks things off by sharing a fascinating anecdote about how he ended up designing an analog SAR during his winter holiday in the Norwegian mountains, sparked by the opportunity to include analog designs on Tiny Tapeout 6. The conversation then shifts to Carsten’s thoughts on the accessibility of 130nm technology for analog design, which he be...| Articles on Zero to ASIC Course
Hi and happy new year! Welcome to my year in review video of 2023. We’ll revisit the biggest moments of open source semiconductors, the goals I failed and those I met, and set some new ones for 2024! So, let’s start with the biggest news of 2023. Last year saw the end of the Google sponsored lottery shuttles. We were expecting around another 8 shuttles for sky130, GF180 and the start of sky90.| Zero to ASIC Course
I’ve just updated the VGA clock PCB to take advantage of a batch of new chips. I think my VGA clock design might be the world’s first certified open source hardware down to the chip level. Unfortunately the MPW1 chips were very hard to use and the new ones have a different pinout and footprint. I’ve been using the clock design as a test project for all the Tiny Tapeout chips past TT03.| Zero to ASIC Course
The EU and US have pledged $100B investment in semiconductors with their chips acts. A huge percentage will go to building new fabs, but both acts acknowledge that factories are no use without trained people to run them. The NSF commissioned a report on research, education and workforce development - recently delivered by Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David Harris, Rajit Manohar, Pinaki Mazumder, Larry Pileggi & James Stine.| Zero to ASIC Course
For the last few years I’ve worn an old 4 inch wafer to conferences or whenever I’m teaching in person. People rarely get to handle a wafer and are always interested to know more. While it’s a fantastic conversation starter, the problem with this necklace is that it’s too hip-hop, and not enough “15 million dollar Nikon Lithography Stepper”. To resolve this annoyance, I decided to make the most ridiculous ASIC bling possible - using my own chips of course!| Zero to ASIC Course
We submitted Tiny Tapeout 2 back in December, and last week I received the chips from Efabless. Most first chip designs fail, but you never hear about it because the big companies keep it a secret. So we thought - why not do the world’s first public silicon bring up? Thankfully the chips worked, and you can watch the whole stream here. We’ve since found 1 errata, but luckily not a show stopper.| Zero to ASIC Course
I’m very happy to have over 140 designs from 30 countries submitted to Tiny Tapeout 4! Top level statistics: Total standard cells 82126 Maximum cells used was 6813 for project 033 Maximum utilisation was 87.18% for project 016 Total wire length was 2607 mm Thanks to everyone who submitted and all the contributors. Also a huge thanks to Efabless Corporation for sponsoring the project! Tiny Tapeout 5 is already open and will close in early November 2023.| Zero to ASIC Course
The Free Silicon Conference returned to Paris in 2023. There were plenty of great talks and I really enjoyed the conference. I was able to interview the organiser and several speakers: Luca Alloatti - organiser Thomas Benz - PULP Jørgen Kragh Jakobsen - his work on open source silicon in Denmark Thomas Parry - startup founder of Spherical Systems Rene Scholz - Open source PDK from IHP Microsystems Dan Fritchman - Analog tools Harald Pretl - Mixed signal design You can find all the recorded t...| Zero to ASIC Course
I got a once in a lifetime chance to use a particle accelerator to look inside my first ASIC! It was amazing to be able to see all the different layers and match them up with the design files I sent to Efabless. So join me on my journey to the Swiss Light Source at the Paul Scherrer Institut where I learnt how they use their synchrotron to make some awesome images!| Zero to ASIC Course
I had the chance to interview Eric Schlaepfer about his MOnSter 6502, a 6502 processor made out of discrete transistors. For me, one of the most interesting things about this project are the similarities to ASIC design, for example Eric wrote his own LVS tool. You can find out lots more at his website. Here’s the visual 6502 simulator. You can also hear other interviews with Eric over at The Amp Hour and The unnamed reverse engineering podcasts.| Zero to ASIC Course
Harald Pretl made a fascinating submission to Tiny Tapeout 3, an analog circuit made from digital standard cells. It builds a DAC out of a lot of tristate inverters, and a big capacitor by ganging up a lot of NAND gates. In this interview with Harald we discuss how it works and how he made it and simulated it. You can check his design here, including the source and GDS.| Zero to ASIC Course
The OpenROAD GUI is a great way to explore your ASIC design. You can: View various types of heatmaps, including Placement density Power density Routing congestion IR drop Trace nets, View the clock tree, Inspect timing and more. I recently spoke with Matt Liberty, and OpenROAD maintainer, and he showed me how to inspect a simple design. OpenLane If you’re using OpenLane to harden your ASIC designs, and you want to use the GUI, you might hit a segfault.| Zero to ASIC Course
Welcome to my highlights from 2022! It was a big year for open-source silicon, especially the Zero to ASIC course and TinyTapeout. Let’s look at some of the highlights and then some aims for 2023. Here are a few of the highlights: Four Zero to ASIC course tapeouts: MPW5, MPW6, MPW7, and MPW8 Rolled out TinyTapeout 01 and 02, helping nearly 250 people tapeout their designs, I personally submitted my 19th tapeout Presented and hosted a TinyTapeout workshop at the Hackaday SuperCon in Novemebe...| Zero to ASIC Course
ASIC development tools have often been inaccessible due to cost and complexity. Even as free, open-source tools have become available, the complexity of building and installing the tools has slowed their use by would-be designers. A challenge in making ASIC development more accessible has been to provide free, easy-to-use development tools. Thankfully development of cloud-based tools using open-source software are making chip design easier than ever. In June 2022, I had the chance to talk wit...| Zero to ASIC Course
An exciting new opportunity for developing open-source silicon reached fruition at the end of 2022! GlobalFoundries (GF) teamed up with Google to fund open-source projects using GF’s foundry and their open-source 180nm PDK GF180. Open-source PDKs like GF180 and Skywater 130nm are essential for making silicon design more accessible. To now have GlobalFoundries involved with fabricating designs will hopefully mean increased opportunities to turn designs into silicon. GF180’s first multi-pro...| Zero to ASIC Course
Using the Tiny User Project tool, people can quickly submit a Tiny Tapeout design to the MPW lottery. The low barrier to entry makes this a great tool to try variations on a design, test faster I/O speeds on an MPW tapeout, or simply compare tapeout processes using a different submission venue. @Proppy developed the an easy-to-use tool as an extension to the Tiny Tapeout flow. Proppy’s template repository uses GitHub actions to add a design to the Efabless Caravel User Project.| Zero to ASIC Course
I’m happy to announce that TinyTapeout02 was successfully submitted for manufacture in December 2022! 164 designs were included on the tapeout. Update! TinyTapeout 2 chips are back and working! If you’re unfamiliar, TinyTapeout is an educational project that makes it easier and cheaper than ever to get your digital designs manufactured on a real chip! We had a first trial, TinyTapeout01 in September 2022 that was destined for MPW7. TinyTapeout01 helped establish a baseline architecture fo...| Zero to ASIC Course
I am excited to introduce a grant for the Zero to ASIC course. The grant will provide a Silicon-level ticket for selected participants. Two grants will be awarded per month. Course goals This course aims to revolutionize open-source silicon by training engineers, hobbyists and enthusiasts to make their own ASICs. During the course, you will design a circuit that will be submitted to the Google lottery MPW to be manufactured in silicon!| Zero to ASIC Course
We submitted for MPW8! Special congratulations to Adrian Wong for the course submission! We still managed to get 4 projects in the submission…not bad for a deadline of New Year’s Eve. The projects include a partial implementation of an L1 GPS tracking channel by Adrian Wong, a Simon Says game implementated by Uri Shaked, and 2 demo submissions (frequency counter and RGB mixer) from me. Here’s the github repo for the group submission and the Efabless project.| Zero to ASIC Course
SiliWiz will help you get a basic understanding of how semiconductors work and are manufactured at a fundamental level. It’s a free and open source tool that you can play with in your browser. Aims Draw your own logic gate and understand how that gate would be manufactured in a foundry. Learn how the gate is built out of the fundamental circuit elements used in chip design Understand how the drawings are used to manufacture the chip Be aware of some of SiliWiz’s limitations and simplifica...| Zero to ASIC Course
The 3D structures created within a silicon die are spectacular to see. Thanks to Maximo (@maxiborga on Twitter), there’s now a video for 3D rendering ASIC designs enabling anyone to convert their ASIC design into a beautiful 3D rendering. 3D-rendered chip in Blender His walkthrough shows how to convert GDS to STL files, enabling you to import the files in image editing software like Blender. By following along the video, I was able to render my first ever GDS, an inverter I created back in ...| Zero to ASIC Course
ASICs pack in billions of transistors per square centimeter, making their construction and functionality impossible to understand with the naked eye. In fact, the upcoming 2 nanometer technology will be so small* that the transistor dimensions will only be 20X larger than an individual atom. Wouldn’t it be great to see how ASICs are built in 3D at a scale that our bulky human hands can appreciate? Well wait no longer!| Zero to ASIC Course
Proppy has been doing some great work with preparing the open source ASIC tools to work inside Jupyter notebooks. This means that you can now experiment with simulation and ASIC hardening without needing to download or configure the tools. I think this is going to be of great importance for academia and education: Now when people publish papers they can include a link to a notebook that reproduces the published results.| Zero to ASIC Course
Teodor-Dumitru Ene has been doing some interesting work on optimising hardware adders. Until I spoke with him, I didn’t realise how important this basic digital building block really is. An interesting statistic from his presentation slides: When a RISC-V processor boots into Linux, 65% to 72% of instructions use addition. By default, Yosys will synthesise something like this: reg [31:0] a; reg [31:0] b; wire sum = a + b; Using a ‘middle of the road’ adder, that gives medium PPA (power,...| Zero to ASIC Course
Yes! All the designs I submitted to MPW1 are working: ✅ 7 segment display ✅ TPM2137 CTF ✅ WS2812 led driver ✅ VGA clock ✅ Multiplexor I put together a video to demonstrate them all: The 4 other designs that were part of this submission were made by friends who I’ve now sent samples to. It’s looking likely that everyone’s designs will work. Bringup You can read more about the bringup process here, and see the repository with firmware here: https://github.| Zero to ASIC Course
I interviewed Anton Blanchard about his MPW1 application - a 64bit OpenPOWER core written in VHDL. We talked about: VHDL vs Verilog FPGA vs ASIC Problems they faced with such a big design SRAM vs DFFRAM Software vs Hardware mentality Fixing bugs and contributing to OpenLane You can check out the repository here: https://github.com/antonblanchard/microwatt-caravel| Zero to ASIC Course
MPW1 seems an age ago, we submitted in December 2020, but it needed some last minute DRC fixes in February. Silicon was received a few weeks ago, and unfortunately we have some serious issues that will prevent most designs from working. This appears to be due to a bad clock tree in the management section of the chip. Additionally, OpenSTA, the tool meant to verify the clock tree was also misconfigured.| Zero to ASIC Course
In this interview with Matt Guthaus, we talk about: Recap - what is OpenRAM Why do we need a memory compiler like OpenRAM? 3 phases of OpenRAM development What’s changed since FOSSi dialup MPW2 tapeout of OpenRAM Test modes What was hard about MPW2 DRC issues Status of OpenLANE support for OpenRAM Future plans for OpenRAM Access to resistive RAM, hopefully for MPW4 Resources WOSET link: https://woset-workshop.github.io/ MPW2 application: https://platform.efabless.com/projects/187 FOSSi dial...| Zero to ASIC Course
Tom Spyrou is a long time EDA developer who has worked at large and small companies. In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation. He was the original architect of PrimeTime STA algorithm. Manager of Cadence Common timing Engine and precursor to Open Access Senior technical positions at Synopsys, Cadence, Simplex, AMD, Altera and Intel.| Zero to ASIC Course
I’m very pleased to get OSHWA certification for my ASIC clock. Who knows, maybe this is a world first! The clock was submitted as part of MPW1. We’re expecting silicon back in August/September, so it was time to get the PCB ready and try to source the other components! I started off by forking Sam Littlewood’s carrier board. This is a 4 layer board, but as I don’t need all the signals I was able to get it down to 2 layers for cheaper fabrication.| Zero to ASIC Course
One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1. In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them. Dirk & Nguyen kindly allowed me to interview them about: their FABulous eFPGA framework, support for Yosys & NextPNR, parameterisation of the fabric, blockrams with OpenRAM, the...| Zero to ASIC Course
After 6 months, 90 participants and 14 designs submitted to MPW2, I’m making the Zero to ASIC course even better! One of the things that’s great about the course is that you can proceed at your own pace. I originally set the course length at 6 weeks, but a lot of people want more time than this. To resolve this I have: removed the expiry date on the discord support, removed the expiry date on office hours.| Zero to ASIC Course
There continues to be a lot of interest about analogue design with the open source PDK. To cover this interest, I’ve previously interviewed: Diego about his opamp, Lakshmi about her PLL and Thomas about his satellite transceiver. One of the big changes in MPW2 was the provision of more analogue support in the form of Caravan - a new harness. This is exciting because one of the key advantages of an ASIC over an FPGA is the mixed signal capability.| Zero to ASIC Course
Caravel is the name of the harness provided by Efabless to make it easier to submit a design to the foundry. Among other things, it provides: The padring 3kB of memory A small RISCV processor called PicoRV32 GPIOs A logic analyser A Wishbone bus For the full details, check the documentation The simplest way to interface between your project and the PicoRV32 is probably the logic analyser. This gives you 128 ins and outs that you can use to configure or debug your design.| Zero to ASIC Course
Efabless have announced MPW2! The closing date is the 18th of June. The biggest changes are: OpenLANE ASIC flow updated to rc0.15 Caravel has become caravel_user_project at the mpw-two-c tag: smaller repo size includes a ‘Caravel Lite’ submodule new IRQ ports logic analyser registers renamed An alternative analogue specific ‘Caravan’ harness The submission process has been streamlined to make it faster and easier to submit You can browse the current applications here: https://platform.| Zero to ASIC Course
In this interview Dan and I talk about his submission to the first shuttle, simulating video projects, how to do graphics with no frame buffer and the joys of retro gaming. Caravel repo: https://github.com/dan-rodrigues/caravel_vdp_lite IceStation32: https://github.com/dan-rodrigues/icestation-32| Zero to ASIC Course
OpenLANE makes a lot of output files! This can be quite confusing when you’re getting started. Here’s a useful spreadsheet I made to show: the path of the files most important files and what they mean which tool creates which file Thanks Amr and Ahmed for helping me with this! The spreadsheet was updated for MPW2, and there haven’t been major changes in MPW3. OpenLANE summary tool I’ve also made a summary tool: https://github.| Zero to ASIC Course
In this interview Thomas talks us through his Amateur satellite transceiver shuttle submission. We also discuss the differences between the Open Source tools and the industry standard ones he uses in his day job. Design repo: https://github.com/yrrapt/amsat_txrx_ic Caravel repo: https://github.com/yrrapt/caravel_amsat_txrx_ic Connect with Thomas on linkedin: https://www.linkedin.com/in/thomas-parry-60419468/| Zero to ASIC Course
I’ve been wanting to try plotting or printing the GDS files from my first ASIC for a while, and finally I’ve had some time to have a play. I used KLayout because it’s easy to change colours, show and hide layers, and export to a high resolution PNG. I want to make a poster with 3 pictures inside: The whole chip, Zoomed into the VGA clock macro, Zoomed into the standard cells.| Zero to ASIC Course
When I was first testing my designs inside Caravel, I was quite confused about all the GPIO options. Each pin has a range of options that can be configured by firmware running on the RISCV processor. Each pin can be driven from the processor or your custom design. The outputs have separate output enable lines for bi-directional signalling. I put together an experiment where I tried the most important options and checked the results in a simulation.| Zero to ASIC Course
The story of the first Open Source ASIC shuttle continues! A few of the applicants to the first shuttle were recently contacted by efabless - they had discovered some DRC issues that couldn’t be waived by the foundry. In my recent interview with Tim Edwards, he mentioned that Google are paying for a license of Calibre - another swiss army ASIC tool like Magic. This is to help make sure that the OpenLANE DRC hasn’t missed anything.| Zero to ASIC Course
In this interview I talk with Tim Edwards from eFabless. He is their vice president of analog and platform. We mostly talked about what needs to happen before they send the final files to Skywater. A lot of the work is infrastructure: fetching files, compositing IDs, generating fill layers, a final DRC run.| Zero to ASIC Course
In this interview I talk with Lakshmi S about their shuttle submission. As well as convering what a PLL is and its component parts, we also answered some interesting questions from the twitter community: how long things take to design, what is fun and what is frustrating, how to change the PLL’s response, why design a integrated loop filter, process corners and ngspice post silicon testing. The repository is here.| Zero to ASIC Course
In this interview I talk with Diego Hernando about their ASIC submission. They have been working on some analog blocks; mostly op-amps but also including a PLL from another designer. We discuss the difference between digital and analog design, the tools, simulation, layout and testing. Here’s the link to the repository| Zero to ASIC Course
In this interview I talk with Arya Reais-Parsi about their shuttle submission. They are working with a group of students to create Open Source FPGA fabric that can be put on an ASIC and configured with yosys/nextpnr. The repository is here.| Zero to ASIC Course
In this interview I talk with Sylvain ’tnt’ Munaut about his Google/Skywater ASIC application. The design is especially interesting to me because of the way it merges the SRAM blocks with the logic. This has been a major challenge in my own design. Here’s the link to the repository| Zero to ASIC Course
In this interview I talk with Vladimir Milovanović about putting a spectrometer on the Google/Skywater/Efabless ASIC shuttle. He created the design using Chisel. The repository is here.| Zero to ASIC Course
The Google / Skywater shuttle reserves about 10 square mm (10 million square microns) of space for your design. This comparison that Mohamed from efabless put together shows the various areas (and time to generate the GDS2 files) of some popular designs. We could fit in about 10 picorv32 RISCV cores! My designs I currently have 3 designs ready to add to the multi project harness: Name Square microns How many would fit?| Zero to ASIC Course
Image attributions for images used on this website. Image from Mohamed Shalan Image from Caravel Datasheet Image from RFCafe Image from Caravel Datasheet Image from Wikipedia Image from Components 101 Image from Wikipedia Image from WhaTech Image from Technocrazed Image from Zeptobars Image from Lattice Semiconductor Image from Lattice Semiconductor Image from M. Rovitto Image from Texplained Image from Wikimedia Image from Europractice Image from VLSI Systems by Mead & Conway| Zero to ASIC Course
Welcome to the September 2022 monthly update! Here are the main topics from last month: MPW7 submission, MPW2 updates, Job posting at E-Fabless, New videos, Is it the end for UVM? and Rendering GDS files with Blender or in your browser MPW7 The deadline for MPW7 was the 14th of September and the Zero to ASIC course submitted another set of projects. Special shout out to Farhad, Peng and James who are all first time tape outs on the project.| Zero to ASIC Course
In this interview with Professor James Stine, we talk about: Why is Open Source the key to innovation? What do students struggle with most when learning to design standard cell libraries? What are the biggest misconceptions engineers have about standard cells? What’s James’ tool flow? How many cells are needed to make a library? Why do we need another library for Global Foundries (GF) 180? How far are open source tools from commercial tools?| Zero to ASIC Course
We submitted for MPW7! I am particularly excited about this submission because we were able to submit the Zero to ASIC course designs as well as the first TinyTapeout design. MPW7 has by far had the most submissions of the MPW shuttles so far with 72 submitted projects as of 13 September. Congratulations to everyone on the course submission! We had 9 projects from the course, with 1 demo arbitrary function generator from me, a 32-bit RISC-V based processor by Farhad, an in silicon version of ...| Zero to ASIC Course
Following my interview with Teo on optimising hardware adders, I thought it would be a great project to tapeout on MPW6. I wrote about the process on twitter: I'm working on putting @td_ene 's adder work onto MPW6. Work in progress repo here: https://t.co/OBg8jQG1HJ It was very easy to generate the adders, but I'm getting stuck on instrumenting them. I need to measure the performance inside the chip to get accurate results.| Zero to ASIC Course
We submitted for MPW6! We had 4 submissions from the course, the shared SRAM infrastructure, and I did some work on instrumenting Teo’s hardware adders. Congratulations to: Zorkan ERKAN Emre Hepsag Gregory Kielian Jason K. Eshraghian for getting your first ASIC designs on the submission! We also had some people from the course make personal applications for a whole chip: Shumpei Kawasaki - MARMOT SOC Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses, Prop...| Zero to ASIC Course
We submitted for MPW5! We had 8 submissions from the course, the shared SRAM infrastructure, and I updated my demo designs. We also had some people from the course make personal applications for a whole chip: Steve & Zhenle - PSRAM (HyperRAM) interface with an ACORN PRNG, Q3K - simple, microcontroller-style SoC based around a Lanai core, Maximo - Hardware implementation of the Hack Computer from the Nand to Tetris courses, Zbigniew - A rendering circuit for three blobs and a playable tetris c...| Zero to ASIC Course
Wow! What a journey. I’m very happy to announce our submission is in and accepted. Now we have a long wait to see if it works! (it does! Jump to the end for an update). Here’s a picture of the final design. The outer edge and the block at the bottom are all part of Caravel, the standard chip format that everyone on the shuttle has to use. It includes a RISCV processor, RAM, UART, a wishbone bus and more.| Zero to ASIC Course
Almost exactly a year ago in March 2020 I started getting interested in Open Source ASIC tooling. I don’t remember exactly what sparked my interest, but I remember this talk by Tim Edwards at WOSH: Bootstrapping a real working design flow and sometime after seeing Adam Zeloof posting a picture of an ASIC implementation of pong. I began by investigating QFlow. The standard cells used by QFlow were from Oklahoma State University (OSU).| Zero to ASIC Course
We did it! 14 people from the course got their designs into the group submission, and the project was accepted for fabrication. Silicon here we come! You can get all the details on all the projects submitted to MPW2 here - you’ll need to select the MPW2 filter. And see how I put the application together here, with the repo here. Project listing RGB Mixer Author: Matt Venn Github: https://github.com/mattvenn/wrapped_rgb_mixer/tree/caravel-mpw-two-c Description: reads 3 encoders and generates...| Zero to ASIC Course
We submitted for MPW3! The tapeout date was delayed by a couple of weeks due to issues with the toolchain. Update! We received silicon in June 2023 (18 months later!) and I was able to get both my designs partially working. MPW3 We had 7 new submissions from the course, 4 repeats from MPW1 and 2 with fixed clock trees, a new wishbone demo from me and the OpenRAM block.| Zero to ASIC Course
We submitted for MPW4! I was pretty pleased we managed to get so much in with such little time and for a tapeout date of New Year’s Eve. We had 9 submissions from the course, with 1 demo project from me and a new version of Maximo’s hacksoc. Uri submitted 3 designs including some custom standard cells in the shape of skulls! We also implemented the shared SRAM, which means that the group projects have access to a local fast memory (like a blockram on an FPGA).| Zero to ASIC Course
I have slowly been learning how to use Github actions to help me build microchips. It’s harder than it should be to get a working toolchain up. There are lots of repositories, submodules, docker images, environment variables, and they all have to be exactly right. If not, either the flow won’t work correctly, or you’ll make some GDS that will fail the precheck or tapeout tests. For the course, I have a VM and a set of instructions to do a manual install.| Zero to ASIC Course
I submitted my first ASIC designs to the free Google shuttle in December of 2020. In October 2021, we heard there were serious clock related problems with the management area of the chip due to issues with the toolchain. It seemed unlikely that anyone would be able to get anything beyond a single blinking LED from MPW1. The hold violations in the management system meant that the PicoRV32 cpu couldn’t run and setup the GPIOs.| Zero to ASIC Course
