Unleashing Heterogeneous Compute: Lessons From Real-World System Design
By profiling systems early, designers can address fundamental issues in data flow and resource coordination.| Semiconductor Engineering
A new technical paper titled “2025 Most Important Hardware Weaknesses” was published by researchers at Hardware CWE Special Interest Group. Excerpt “The Most Important Hardware Weaknesses (MIHW) empowers organizations with the knowledge to proactively strengthen hardware security and reduce risks at the source. The 2025 CWE MIHW represents a refreshed and enhanced effort to identify... » read more The post 2025 Critical Hardware Weaknesses (Hardware CWE Special Interest Group) appeared...| Semiconductor Engineering
A new technical paper titled “Exploring Electrochemical Methods for Precision Stress Control in Nanoscale Devices ” was published by researchers at the University of Bristol. Abstract “Tuning the local film stress (and associated strain) provides a universal route toward exerting dynamic control on propagating fields in nanoscale geometries and engineering controlled interactions between them. The... » read more The post Electrochemical Absorption of Hydrogen in Structured Palladium Th...| Semiconductor Engineering
A new technical paper titled “MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging” was published by researchers at the University of Minnesota – Twin Cities. Abstract “As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarchies. To... » read more The post LLM-Based Chiplet Design Generation Framework (Univ. of Minneso...| Semiconductor Engineering
China ramps domestic AI ICs; Anthropic warns of agentic AI weaponization; 321-layer NAND flash; IBM-AMD integrate HPC/quantum; Intel CEO wins Kaufman Award; traffic-jam assistance errors; Amkor preps massive U.S. packaging/test plant; Rapidus-Keysight 2nm GAA PDK. The post Chip Industry Week in Review appeared first on Semiconductor Engineering.| Semiconductor Engineering
A new technical paper titled “Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System” was published by researchers at Rensselaer Polytechnic Institute and IBM. Abstract “Large Language Model (LLM) inference is increasingly constrained by memory bandwidth, with frequent access to the key-value (KV) cache dominating data movement. While attention sparsity reduces some... » read more The post Dynamic KV Cache Scheduling in Heterogeneous Memory Systems for...| Semiconductor Engineering
A new technical paper titled “Power Stabilization for AI Training Datacenters” was published by researchers at Microsoft, OpenAI, and NVIDIA. Abstract “Large Artificial Intelligence (AI) training workloads spanning several tens of thousands of GPUs present unique power management challenges. These arise due to the high variability in power consumption during the training. Given the synchronous... » read more The post Power Stabilization To Allow Continued Scaling Of AI Training Workloa...| Semiconductor Engineering
The economics associated with current AI development do not add up. Lots of money is spent, but little money is earned. The post AI Effort And Money Misplaced appeared first on Semiconductor Engineering.| Semiconductor Engineering
From node selection to choice of interconnect, multi-die system designers face a myriad of decisions. The post Chiplet Design Considerations appeared first on Semiconductor Engineering.| Semiconductor Engineering
Validate FEC performance in a wide variety of real application scenarios prior to widespread deployment. The post Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction appeared first on Semiconductor Engineering.| Semiconductor Engineering
By profiling systems early, designers can address fundamental issues in data flow and resource coordination.| Semiconductor Engineering
How AI is reshaping EDA, and how it will help chipmakers to focus on domain-specific solutions.| Semiconductor Engineering
Broad-line supplier of EDA, IP and software testing tools.| Semiconductor Engineering
Mentor, a Siemens Business, is a broad line EDA supplier. It provides a complete semiconductor design flow that includes simulation, emulation, place and route, verification, design for manufacturing, and test. It also develops tools for wire harness systems and computational fluid dynamics.| Semiconductor Engineering
A full line EDA supplier| Semiconductor Engineering
Baya Systems offers a software-defined, unified fabric for SoCs and chiplets that provides a common transport with support for multiple protocols and coherency needs within a unified design flow. Baya Systems’ NoC is topology-agnostic, and its software enables continuous refinement of data-driven architecture and micro-architecture development from initial specification through post-silicon tuning, with built-in simulation... » read more| Semiconductor Engineering
ChipAgents develops AI agents for EDA workflows to boost RTL design, debugging, and verification productivity. Its ChipAgents AI chip design environment enables designers to transform concepts into precise design specifications using simple language prompts, analyzes and generates RTL design specs and code, auto-completes Verilog, automates the creation of testbenches, and autonomously verifies and debugs design... » read more| Semiconductor Engineering
Why and where limitations are needed in AI-driven design, and where software-defined hardware works best.| Semiconductor Engineering
Narrowly defined verticals offer the best opportunities for AI. Plus, what will the impact be on junior engineers?| Semiconductor Engineering
A small crack early in the fabrication process has the potential to grow into a killer defect later.| Semiconductor Engineering
Measuring how injected faults propagate through a design and how long they remain in the system.| Semiconductor Engineering
Conference presentations tackle emerging challenges in photomasks and lithography.| Semiconductor Engineering
PDF Solutions develops yield-improvement technologies and services for the manufacturing process lifecycle. The company’s focus is accelerating fab yield ramp, electrical characterization for production control, and big data analytics software for fabless, foundry, test and assembly production control and monitoring. Electrical characterization is becoming increasingly important because traditional optical inspection cannot see defects that are... » read more| Semiconductor Engineering
Throughput remains an issue. A solution will require a combination of technologies.| Semiconductor Engineering
Deep insights into the increasingly complex task of designing, testing, integrating, and manufacturing semiconductors. Explore the latest in Semiengineering and cutting-edge chip technology.| Semiconductor Engineering
Next-generation optical inspection is about more than just sensitivity. It’s about reliably seeing through complexity.| Semiconductor Engineering
Companies are selecting preferred flows, but the process details are changing rapidly to meet the needs of different applications.| Semiconductor Engineering
Brewer Science develops materials and processes for semiconductor, including anti-reflective coatings to control light during photolithography, materials for packaging chips, protective coating, bonding/debonding materials for fan-out wafer-level packaging, and carbon-based sensors.| Semiconductor Engineering
But blazing fast data speeds come with significant manufacturing challenges.| Semiconductor Engineering
ECTC progress report on enabling technologies, including cooling chiplets, 1µm hybrid bonding, RDL buildups, and co-packaged optics.| Semiconductor Engineering
3D-IC trends and challenges; virtual prototypes for SDVs; chiplet security; sustainable AI development; quality best practices.| Semiconductor Engineering
Effective collaboration across the supply chain is crucial for achieving carbon reduction goals.| Semiconductor Engineering
Enabling 6G: Superlattice castellated FETs; compact phased-array transceiver; RF GaN-on-Si transistor.| Semiconductor Engineering
Catch mistakes early, confirm exceptions are used correctly, and ensure constraints involve in step with the RTL.| Semiconductor Engineering
IC, AI global ranking; China's fully automated IC design system; Micron goes bigger; PCIe 7.0 spec; TSMC-Tokyo joint lab; panel-level packaging win; first neuromorphic compute system; GAA forksheets; AMD's new GPUs.| Semiconductor Engineering
A new technical paper titled “QiMeng: Fully Automated Hardware and Software Design for Processor Chip” was published by researchers at Chinese Academy of Sciences. Abstract “Processor chip design technology serves as a key frontier driving breakthroughs in computer science and related fields. With the rapid advancement of information technology, conventional design paradigms face three major... » read more| Semiconductor Engineering
Addressing a variety of complex issues early in the design cycle can save time on the back end, speeding time to market with better quality.| Semiconductor Engineering
How verification solutions are being applied to real-world challenges.| Semiconductor Engineering
High bandwidth and low latency are paramount for AI-powered edge and endpoints.| Semiconductor Engineering
GF's new partnerships; HP's MEMS funding; CHIPS Metrology Community; Hot Chips highlights; 1c DDR5; Accellera's new standard; AI's role in chip design; chiplets; more earnings.| Semiconductor Engineering
Keysight Technologies is a test and measurement equipment company. It develops advanced design and validation solutions that span the development lifecycle, including design simulation, prototype validation, automated software testing, manufacturing analysis and network performance optimization and visibility in enterprise, service provider and cloud environments. Customers span worldwide communications and industrial ecosystems, aerospace and defense, automotive,... » read more| Semiconductor Engineering
SRAM uses bistable latching circuitry to store each bit. While no refresh is necessary it is still volatile in the sense that data is lost when the memory is not powered. A typical SRAM uses 6 MOSFETs to store each memory bit although additional transistors may become necessary at smaller nodes. Fig 1. Simplified block... » read more| Semiconductor Engineering
ANSYS develops specialized system-level simulation technology for a variety of industries.| Semiconductor Engineering
Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.| Semiconductor Engineering
AI and robotics are taking on bigger, more complex, and increasingly autonomous tasks, but integration with existing equipment and processes remains a formidable challenge.| Semiconductor Engineering
Universities, companies, and governments are forming broad partnerships to update skills and foster innovation in chips, security, AI, and related fields.| Semiconductor Engineering
Discrete unpackaged die that can be assembled into a package with other chiplets; each chiplet is optimized to its function.| Semiconductor Engineering
High-bandwidth memory (HBM) is standardized stacked memory technology that provides very wide channels for data, both within the stack and between the memory and logic. An HBM stack can contain up to eight DRAM modules, which are connected by two channels per module. Current implementations include up to four chips, which is roughly the equivalent... » read more| Semiconductor Engineering
Slated for 2.5nm and beyond, complementary FET (CFET) is a more complex version of a gate-all-around device. Traditional gate-all-around FETs stack several p-type wires on top of each other. In a separate device, the transistor stacks n-type wires on each other. In CFETs, the idea is to stack both nFET and pFET wires on each... » read more| Semiconductor Engineering
Published 8/23/2021 (by Mark LaPedus & Ed Sperling). . “Inside Intel’s Ambitious Roadmap” article link is here. Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of... » read more| Semiconductor Engineering
Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.| Semiconductor Engineering
